The invention pertains most broadly to a compensated current switch emitter-follower (CCSEF) logic network having a reduced signal swing and, correspondingly, a reduced circuit delay time. More specifically, the invention pertains to such a logic network in which UP and DOWN logic levels are controlled so as to be precisely symmetrical around a reference level at all times. Yet more specifically, the invention pertains to such a logic network in which a reference voltage is supplied from "off-chip", while logic signal swings are held to a narrow range without affecting the noise margin of the various circuits which make up the network.
Compensated current switch emitter-follower logic circuits have been known for some time. An example of such a logic circuit is described by Muller et al., "Fully Compensated Emitter-Coupled Logic: Eliminating the Drawbacks of Conventional ECL", IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973, pp. 362-367, and shown in FIG. 1 herein. In this circuit, input transistors 13 and 14 are coupled in parallel with one another. The bases of the transistors 13 and 14 are connected to input terminals IN 1 and IN 2 to which two input logic signals are applied. The commonly connected collectors of the transistors 13 and 14 are coupled through a resistor 22 to a terminal to which a positive power supply voltage V.sub.CC is applied. The transistors 13 and 14 are connected in a differential amplifier configuration with a third transistor 18, the collector of which is coupled through a resistor 21 to the V.sub.CC terminal. The base of the transistor 18 is connected to a logic level reference potential V.sub.R, here assumed to be ground although other potentials may be used. Diodes 19 and 20 are connected back to back between the collector of the transistor 18 and the commonly connected collectors of the transistors 13 and 14 through a resistor 15. The emitters of all three transistors 13, 14 and 18 are connected to the collector of a transistor 16, the latter device serving as a constant current source for the differential amplifier circuit. The emitter of the transistor 16 is connected through a resistor 17 to a power supply terminal to which a negative supply voltage V.sub.EE is applied. A reference voltage V.sub.CS is applied to the base of the transistor 16. Varying V.sub.CS will cause the UP and DOWN output logic levels to simultaneously vary. Two output transistors 11 and 23 are provided, both of these being connected in an emitter-follower configuration with their emitters coupled through resistors 12 and 24, respectively, to a fixed potential V.sub.T. The base input to the transistor 11 is supplied from the commonly connected collectors of the transistors 13 and 14, while the base input to the transistor 23 is supplied from the collector of the transistor 18. The emitters of the transistors 11 and 23 are connected to output terminals OUT 2 and OUT 1, respectively.
In operation, when at least one of the input signals applied to the terminals IN 1 and IN 2 is in the UP (positive) state, the corresponding transistor 13 or 14 is turned on, thereby causing most of the current which flows through the constant current source transistor 16 to flow through the respective transistor 13 or 14 and the resistor 22. The transistor 18 is then off and the transistor 23 on, thereby causing the output signal on the terminal OUT 1 to be at the UP level. The voltage at the base of transistor 11 is lower than the voltage at the base of transistor 23, and therefore terminal OUT 2 is at the DOWN level. In this manner, the logical OR of the signals on the input terminals IN 1 and IN 2 is produced on the terminal OUT 1 and the logical NOR of those signals on the terminal OUT 2.
The transistor 18 is turned off in the case that an UP level is applied to the base of one of the transistors 13 and 14, in which case the collector of the transistor 18 is pulled in the negative direction by the diode 19. Similarly, when the transistor 18 is on and both the transistors 13 and 14 are off in the case that DOWN-level signals are applied to both input terminals IN 1 and IN 2, the commonly connected collectors of the transistors 13 and 14 are pulled in the negative direction by the diode 20. This limits the voltage swings in the circuit, thereby reducing the switching (delay) times through the circuit.
Ordinarily, there are, of course, many circuits such as the one shown in FIG. 1 on a single integrated circuit chip. In one prior art approach, it was the practice to provide on each chip a reference voltage generator for supplying the voltage V.sub.CS for use by all current source transistors of all logic circuits on the chip. This approach suffers a drawback in that, due to possible variations in the power supply voltage V.sub.CC within a logic network composed of multiple chips, and due to differences among chips such as differences in resistor values or the like, the output UP and DOWN levels may be different for different ones of the chips. This imposes the condition that a relatively large difference between UP and DOWN output levels must be maintained in order to ensure successful communication among chips. In the circuit of FIG. 1, the difference between the UP and DOWN levels is determined by the drop across one of the diodes 19 and 20 plus the drop across the resistor 15. Thus, to provide a sufficiently great difference between the UP and DOWN levels using this prior art technique, the resistor 15 must have a relatively high value.
Various circuits have been proposed for generating a current source control potential such as V.sub.CS in FIG. 1. One simple and straightforward approach is to connect the cathode of a diode to V.sub.EE, and the anode of the diode to the terminal to which V.sub.CS is to be furnished and through a resistor to V.sub.CC. Plural diodes connected in series may be employed. This technique, however, has a drawback in that the V.sub.CS thus generated does not track changes in V.sub.CC. Another approach is simply to connect two resistors in series between V.sub.CC and V.sub.EE in a voltage-divider configuration with the voltage division point connected to the V.sub.CS terminal. Although changes in both V.sub.CC and V.sub.EE can be tracked in this manner, effectively no temperature compensation is provided. In either case, because the value of V.sub.CS produced is not fully compensated for changes in both power supply levels and temperature, the UP and DOWN levels produced by the circuits which employ the current source control potential so generated will tend to shift in a nonsymmetrical manner with respect to the logic signal reference level (ground for the case of the circuit of FIG. 1). This is, of course, an undesirable phenomena in that the noise margin for the circuit is adversely affected.
Accordingly, it is an object of the present invention to provide a logic network employing CCSEF logic circuits in which a single current source control potential generator is provided for a plurality of logic circuits and in which small logic level signal swings can be employed without adversely affecting the noise margin of the various circuits of which the network is composed.
Yet further, it is an object of the present invention to provide such a network in which a single current source control potential generator is provided for a plurality of logic circuits, which current source control potential generator includes compensation for variations in both positive and negative supply voltages as well as for temperature.